The present invention relates to radio frequency identification (RFID) systems, and more particularly to sense amplifiers used in memory modules in RFID transponders.
Radio frequency identification (RFID) is well known using a wide range of base frequencies from about 100 KHz to about 13.5 MHz for passive and active transponders. A passive transponder derives power from the received signal and returns an identification signal. Active transponders contain a power source, typically a battery, and so does not derive power from the received signal. Accordingly, passive transponders require higher signal strength, while active transponders require much less signal strength, but at the cost of a power source.
FIG. 1 is a basic block diagram of an illustrative passive RFID system. Here an interrogation station 100 generates an RF signal 108, usually a pulse signal generated by the logic circuit 104, that is transmitted 110 via an antenna 112 to a transponder (tag) 102. The RF pulse is received via an antenna 114. The antenna 114 connects to an RF impedance matching circuit 116 and to an input/power circuit 118, with means to extract and store energy to power the tag system and means to processes the received signal. The RF signal 110 is rectified to charge a capacitor, not shown, used to power the tag system.
In the simplest RFID systems, the RFID transponder is a passive tag that extracts energy from the radiated wave, thereby providing a load on the RF transmitter. The loading is monitored at the interrogation station and indicates that a tag is present. In such a system there is no need to send any signal back to the interrogation system.
In more complex RFID systems, the transponder contains information that is transmitted back to the interrogation station. Such systems may be found on loading docks where tagged incoming freight, when interrogated, sends back to the interrogation station detailed information about the freight itself. For example, a box containing fragile crystal may inform the interrogation station of that fact. In such systems, referring to FIG. 1, when an RF interrogation signal is received, the input circuitry 118 will transfer the information to a logic circuit 120, typically a microcomputer. The microcomputer retrieves information from memory 126, typically an EEPROM (electrically erasable/programmable memory). The information is fed via a transmitter 122, to the antenna 114 and back 124 to the interrogation station. An EEPROM is used since it can be reprogrammed for other types of relevant information.
The contents of memory are read via a sense amplifier 128 that detects the ones or zeros contained in the memory cells. In such RFID systems, power must be conserved. High read currents and fast read times require high power consumption and generate undesirable noise.
In this document, a logic one is defined as a more positive voltage level and a zero as a less positive voltage level, sometimes called positive logic. It is well known that the logic one/zero designation is arbitrary and the less positive level may be deemed as a logic one, sometimes called negative logic. The present invention applies to both positive and negative logic designations, even if the language refers only to positive logic.
The Federal communications commission (FCC) regulates emissions, so prior art designs provide high power at short range but employ canceling techniques to comply with far range FCC regulations. Suitable techniques are known in the art and are not further discussed herein.
In U.S. Pat. No. 5,999,454 (""454), Smith discloses a current mode sense amplifier for flash memory. This patent and other prior art sense amplifiers referenced in this patent are designed for high speed operation and, so, are high powered. Such circuits generate noise and are, in turn, susceptible to noise problems and are not found in RFID systems.
There is need to minimize power consumption while reading the contents of RFID transponder memory cells. A tradeoff between read time and power dissipation can be made in RFID transponders operating in the lower base-band frequencies since fast read times and the concurrent high read currents are not necessary. Longer read times allow for relatively low read currents that reduce power dissipation and noise generation.
The present invention provides a system and method for reading a sense amplifier in an RFID transponder that operates at low speed and consequently consumes little power.
A first transistor, preferably and MOS type, receives the read current from a memory cell and a parallel transistor provides the mirror of that read current to a charge-storage capacitor. At the beginning of a READ cycle, the capacitor is first discharged. Subsequent mirrored read current then is directed to the capacitor and integrated over a given time period to produce a first voltage. (The capacitor may be a reverse-biased junction diode.)
A comparator circuit is used to compare the first voltage to a second or intermediate reference voltage. This reference voltage is set to lie between the level of a discharged charge-storage capacitor (defined level xe2x80x9czeroxe2x80x9d) and the charged level corresponding to a defined level xe2x80x9cone.xe2x80x9d This second or intermediate voltage may be set in a practical embodiment at about half way between the voltage established by off-state leakage of the memory transistor (zero) and the charged level representing a one.
In a preferred embodiment, a second reference memory cell is used to establish the intermediate voltage. A mirror of the read current from that second memory cell is integrated on a second capacitor forming a second voltage that is input to the comparator. To establish the intermediate reference voltage, several methods can be used. One method would utilize an always conducting reference memory cell, but of only a fraction of the xe2x80x9cstrengthxe2x80x9d or size ratio of the normal memory cells (e.g. using one-half of the channel width or, alternatively, twice the channel length.). A second method would use a full-size always conducting reference memory cell, but adjust the size ratio of the MOS transistors in the current-mirror circuit to reduce the reference voltage to an intermediate value.
In another preferred embodiment a full size or standard second and a third memory cell may be used together with full sized current mirrors and integrating capacitors. In this case the second memory cell is arranged to always output a high current while the third memory cell always outputs a low current. The high current representing a logic one and the low current a logic zero. By averaging the two integrated voltages from the second and the third memory cells the intermediate voltage is formed that tracks the midpoint between a one and a zero in the memory system.
In preferred embodiments, the time period for reading memory contents may range from below one microsecond to ten or more microseconds.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.